Protective structure of semiconductor wafer, method for protecting semiconductor wafer, multilayer protective sheet used therein, and method for processing semiconductor wafer

ABSTRACT

A semiconductor wafer protection structure including a semiconductor wafer and a protective sheet overlaid on a circuit surface of the semiconductor wafer, wherein the protective sheet has a larger diameter than the outer diameter of the semiconductor wafer. Semiconductor wafer protection structures and methods, and laminated protective sheet for use therein are provided and enable prevention of damage to a wafer during grinding and transportation when the wafer is ground to an ultrathin thickness and transported. Also provided is a process for processing a semiconductor wafer whereby damage to the wafer can be reduced during application and cutting of an adhesive sheet.

FIELD OF THE INVENTION

The present invention relates to a semiconductor wafer protectionstructure and method, a laminated protective sheet for use therein, anda process for processing a semiconductor wafer. More particularly, theinvention relates to a semiconductor wafer protection structure andmethod suitably used for grinding a semiconductor wafer to an ultrathinthickness and for storage and transportation of the semiconductor wafer,and also relates to a laminated protective sheet for use in thestructure and method. The invention further relates to a process forprocessing a semiconductor wafer with using the semiconductor waferprotection method.

BACKGROUND OF THE INVENTION

In recent years, the spread of IC cards has been promoted, and furtherreduction of thickness thereof is now demanded. Accordingly, it is nowrequired that the thickness of semiconductor chips, which has been about350 μm, be reduced to 50-100 μm or less. Further, increase of waferdiameter has been studied for improving productivity.

Wafer backgrinding is a conventional step performed after formation ofcircuit pattern. In the wafer backgrinding, a protective sheet isapplied to the circuit surface to protect the circuit surface and to fixthe wafer. The protective sheet used in the backgrinding is previouslycut into substantially the same shape as the wafer to prevent vibrationof the protective sheet during the backgrinding.

The present applicant has made various proposals on the protectivesheets; for example, Japanese Patent Applications Nos. 2001-329146 and2002-67080 propose laminated protective sheets including a rigid filmand a stress relaxation film. The use of such laminated protectivesheets enables reduction of damage to the wafers because the stressrelaxation film reduces the stress occurring during the waferbackgrinding and the rigid film adds strength for wafer transportation.

However, the wafer ground to an ultrathin thickness suffers remarkablylowered strength and is damaged even by a weak impact. For example, aproblem occurs as follows. After the backgrinding, the wafers are storedin a wafer cassette and transported to the subsequent steps. The wafersstored in the wafer cassette are usually transported by hand. Thetransportation often results in chipped wafer edges and cracked wafersby contact of wafer edges to the sidewalls of the wafer cassette.

JP-A-2000-353682 and JP-A-2002-57208 (now JP-A-2003-129011 andJP-A-2003-261842 respectively) disclose techniques wherein a protectivesheet is applied to a semiconductor wafer and is cut into a slightlysmaller size than the maximum wafer diameter, and the wafer is subjectedto subsequent steps such as backgrinding. These techniques can suppress“play” of the protective sheet, so that the vibration of the protectivesheet during backgrinding can be reduced. However, they cannot preventcontact of the wafer edges to the sidewalls of the wafer cassette duringtransportation. Meanwhile, the wafer backgrinding is often followed byapplication of an adhesive sheet to the ground wafer surface for variouspurposes such as formation of a die-bonding adhesive layer. After theadhesive sheet is applied, the protective sheet is peeld to transfer thewafer to the adhesive sheet. Herein, the adhesive sheet applied to thewafer is cut in substantially the same diameter as the wafer. Thecutting of the adhesive sheet is performed by running a cutter along theouter periphery of the wafer. Accordingly, the adhesive sheet can be cutin substantially the same diameter as the wafer. However, the cuttingblade is brought into contact with the outer periphery of the wafer andoften damages the wafer.

DISCLOSURE OF THE INVENTION

The present invention has been made in view of the aforementionedbackground art. It is therefore an object of the invention to provide asemiconductor wafer protection structure and method, and a laminatedprotective sheet for use therein that enable prevention of damage to awafer during grinding and transportation when the wafer is ground to anultrathin thickness and transported. It is another object of theinvention to provide a process for processing a semiconductor waferwhereby damage to the wafer can be reduced during application andcutting of an adhesive sheet.

A first semiconductor wafer protection structure according to thepresent invention comprises a semiconductor wafer and a protective sheetoverlaid on a circuit surface of the semiconductor wafer, wherein theprotective sheet has a larger diameter than the outer diameter of thesemiconductor wafer.

A second semiconductor wafer protection structure according to thepresent invention comprises a semiconductor wafer and a laminatedprotective sheet overlaid on a circuit surface of the semiconductorwafer, wherein the laminated protective sheet comprises a firstprotective layer having substantially the same size as the outerdiameter of the semiconductor wafer and a second protective layerlaminated on the first protective layer and having an outer diameterthat is equal to or larger than the outer diameter of the firstprotective layer, and the laminated protective sheet is overlaid on thecircuit surface via the side of the first protective layer.

In the above protection structures, the protective sheet or thelaminated protective sheet preferably has a maximum diameter that islarger than the outer diameter of the semiconductor wafer by +0.1 to 10mm.

In the laminated protective sheet, the first protective layer preferablyhas an outer diameter that is smaller than the outer diameter of thesemiconductor wafer by −2.0 to 0 mm and the second protective layerpreferably has an outer diameter that is larger than the outer diameterof the semiconductor wafer by +0.1 to +2.0 mm.

In the laminated protective sheet, the first protective layer preferablyincludes a film having a stress relaxation rate of at least 40% after 1minute of 10% elongation, and the second protective layer preferablyincludes a film having a value of Young's modulus×thickness of at least5.0×10⁴ N/m.

A first semiconductor wafer protection method according to the presentinvention comprises overlaying a circuit surface of a semiconductorwafer with a protective sheet having a larger diameter than the outerdiameter of the semiconductor wafer.

A second semiconductor wafer protection method according to the presentinvention comprises overlaying a circuit surface of a semiconductorwafer with a laminated protective sheet, wherein the laminatedprotective sheet comprises a first protective layer having substantiallythe same size as the outer diameter of the semiconductor wafer and asecond protective layer laminated on the first protective layer andhaving an outer diameter that is equal to or larger than the outerdiameter of the first protective layer, and the laminated protectivesheet is overlaid on the circuit surface via the side of the firstprotective layer.

In the first and second protection methods, the protective sheet or thelaminated protective sheet preferably has a maximum diameter that islarger than the outer diameter of the semiconductor wafer by +0.1 to 10mm.

Preferred embodiments of the laminated protective sheet are as describedabove.

A laminated protective sheet for semiconductor wafer according to thepresent invention is a laminate comprising a first protective layer anda second protective layer, wherein the second protective layer has alarger outer diameter than that of the first protective layer.

Preferred embodiments of the laminated protective sheet forsemiconductor wafer are as described above with respect to the laminatedprotective sheet.

The present invention provides the semiconductor wafer protectionstructures and methods, and the laminated protective sheet for usetherein that enable prevention of damage to a wafer during grinding andtransportation when the wafer is ground to an ultrathin thickness andtransported.

A process for processing a semiconductor wafer according to the presentinvention comprises a step comprising backgrinding a semiconductor waferand applying an adhesive sheet to the ground surface while protectingthe semiconductor wafer by the aforesaid semiconductor wafer protectionmethod.

The process for processing a semiconductor wafer generally comprises afurther step to be performed after application of the adhesive sheet,the step comprising:

-   -   cutting off an outer peripheral portion of the adhesive sheet        with a cutter in a manner such that the cutter is moved along an        outer peripheral end surface of the protective sheet or the        laminated protective sheet.

According to the process for processing a semiconductor wafer asdescribed above, a semiconductor wafer is not damaged when an adhesivesheet is applied thereto, and the wafer's end surface is prevented fromcontact with a cutting blade when an outer peripheral portion of theadhesive sheet is cut off. Therefore, the probability that the waferwill be damaged during application and cutting of the adhesive sheet canbe reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view of the first protection structureaccording to the present invention;

FIG. 2 is a schematic sectional view of the second protection structureaccording to one embodiment of the present invention;

FIG. 3 is a schematic sectional view of the second protection structureaccording to another embodiment of the present invention; and

FIG. 4 illustrates a step of the process for processing a semiconductorwafer according to the present invention; wherein:

-   -   1 . . . First protective layer    -   2 . . . Second protective layer (or substrate)    -   3 . . . Pressure-sensitive adhesive layer    -   4 . . . Adhesive layer    -   5 . . . Semiconductor wafer    -   6 . . . Adhesive sheet    -   7 . . . Cutter    -   11 . . . Protective sheet    -   12, 13 . . . Laminated protective sheet    -   A, B, C . . . Semiconductor wafer protection structure

PREFERRED EMBODIMENTS OF THE INVENTION

Hereinbelow, the present invention will be described in greater detailwith reference to the drawings.

As illustrated in FIG. 1, a first protection structure “A” forsemiconductor wafer includes a semiconductor wafer 5 and a protectivesheet 11 overlaid on a circuit surface of the semiconductor wafer,wherein the protective sheet has a larger diameter than the outerdiameter of the semiconductor wafer.

The protective sheet 11 is generally composed of a substrate 2 and apressure-sensitive adhesive (hereinafter “PSA”) layer 3 formed thereon.The substrate 2 may be a multilayered substrate.

That is, as shown in FIG. 2 or 3, second protection structures “B” and“C” for semiconductor wafer include a semiconductor wafer and alaminated protective sheet 12 or 13 overlaid on a circuit surface of thesemiconductor wafer, wherein the laminated protective sheet includes afirst protective layer 1 having substantially the same size as the outerdiameter of the semiconductor wafer and a second protective layer 2laminated on the first protective layer 1 and having an outer diameterthat is equal to (FIG. 2) or larger than (FIG. 3) the outer diameter ofthe first protective layer 1. The laminated protective sheet 12 or 13 isoverlaid on the circuit surface via the side of the first protectivelayer 1.

The semiconductor wafer protection structures having the aboveconstitutions enable the wafers to be stored in a wafer cassette suchthat the end of the wafers 5 is prevented from direct contact with thecassette sidewalls. Thus, damage to the wafers can be prevented. Thatis, the end portion of the protective sheet functions as cushion toprotect the wafer 5. Meanwhile, rigid protective sheet layers aregenerally difficult to peel by a stripping tape. In the presentinvention, the end portion of the protective sheet protrudent outwardfarther than the wafer 5 can work as a lead for peeling. Accordingly,the protective sheet can be easily peeled even if it includes a rigidfilm.

Moreover, when an adhesive sheet 6 is applied to the ground surface ofthe semiconductor wafer 5 after completion of the required step, thewafer 5 is securely protected and is not damaged. Furthermore, asillustrated in FIG. 4, an outer peripheral portion of the adhesive sheet6 is cut in a manner such that a cutter is moved along an outerperipheral end surface of the protective sheet. Accordingly, a cuttingblade 7 is not contacted with the wafer's end surface. Thus, damage tothe wafer can be reduced during application and cutting of the adhesivesheet.

Hereinbelow, preferred embodiments of the present invention will bedescribed in detail. However, it should be construed that the inventionis in no way limited to the embodiments.

The first protection structure A (FIG. 1) according to the inventionwill be described in detail.

The first protection structure A includes the semiconductor wafer 5 andthe protective sheet 11 overlaid on the circuit surface of thesemiconductor wafer, and the protective sheet is larger in outerdiameter than the semiconductor wafer.

The difference in outer diameter between the protective sheet 11 and thesemiconductor wafer 5 ((outer diameter of the protective sheet11)−(outer diameter of the semiconductor wafer 5)) is preferably in therange of 0.1 to 10 mm, more preferably 0.1 to 5 mm, and particularlypreferably 0.1 to 2 mm.

The semiconductor wafer 5 is supported on the protective sheet 11. Whenthe substrate 2 has self-adhesive properties, the semiconductor wafer 5may be supported on the substrate 2 without forming any PSA. It is alsopossible that the semiconductor wafer 5 is supported via the PSA layer3.

The substrate 2 preferably includes a rigid film to achieve sufficientprotective function.

Various thin films are employable as the rigid films. Synthetic resinfilms are preferred in view of water resistance, heat resistance andrigidity. The rigid films preferably have a value of Young'smodulus×thickness of at least 5.0×10⁴N/m, and more preferably in therange of 1×10⁵ to 1×10⁶ N/m. The rigid films generally range inthickness from 10 μm to 5 mm, and preferably from 50 to 500 μm.

Specific examples of the rigid films include polyolefin films such aspolypropylene films and polymethylpentene films, polyvinyl chloridefilms, polyethylene naphthalate films, polyimide films, polyether etherketone films, polyethersulfone films, polystyrene films,polyethyleneterephthalate films, polybutyleneterephthalate films,polyurethane films and polyamide films. The rigid films may besingle-layer films or laminated films of the aforementioned films.

Of the above rigid films, preferred are those that do not cause adverseaffects such as ionic contamination on the wafer. Specifically,polyethyleneterephthalate films, polypropylene films,polyethylenenaphthalate films and polyamide films are particularlypreferred.

On the upper surface of the substrate 2, the PSA layer 3 is provided. Toattain higher adhesion with the PSA layer 3, the upper surface of thesubstrate 2 may be corona treated or may be overlaid with a layer suchas a prime coat.

The area of the PSA layer 3 may be equal to that of the substrate 2, ormay be substantially the same as that of the wafer applied to PSA layer.

The PSA layer 3 on the substrate 2 has a purpose of fixing thesemiconductor wafer 5 during transportation and processing. The PSAlayer 3 may be formed from an energy radiation-curable PSA, or ageneral-purpose, removable PSA containing rubber-based, acryl-based,silicone-based, polyurethane-based or polyvinyl ether-based.

The energy radiation-curable Pressure-sensitive adhesives generallycontain an acrylic PSA and an energy radiation-curable compound as maincomponents.

For example, low-molecular weight compounds having in the molecule atleast two photopolymerizable carbon-carbon double bonds that can beconverted into a three-dimensional network structure by lightirradiation as disclosed in JP-A-S60-196956 and JP-A-S60-223139 arewidely used as the energy radiation-curable compounds incorporated inthe energy radiation-curable Pressure-sensitive adhesives. Specificexamples thereof include trimethylolpropane triacrylate, pentaerythritoltriacrylate, pentaerythritol tetraacrylate, dipentaerythritolmonohydroxypentaacrylate, dipentaerythritol hexaacrylate, 1,4-butyleneglycol diacrylate, 1,6-hexanediol diacrylate, polyethylene glycoldiacrylate, and oligomers such as oligoester acrylates and urethaneacrylates.

With respect to the compounding ratio of the energy radiationpolymerizable compound to the acrylic PSA in the energyradiation-curable PSA, it is preferred that the energy radiationpolymerizable compound is used in an amount of 50 to 200 parts by weightper 100 parts by weight of the acrylic PSA. When this condition issatisfied, the resultant PSA sheet has high initial adhesion anddrastically reduces the adhesion after irradiated with energy radiation.Accordingly, easy peeling can be performed at the interface between thewafer 5 and the energy radiation-curable PSA layer.

The energy radiation-curable PSA layer may be formed from an energyradiation-curable copolymer having an energy radiation polymerizablegroup at a side chain. Such energy radiation-curable copolymers exhibitboth tackiness and energy radiation curing properties. Details of theenergy radiation-curable copolymers having an energy radiationpolymerizable group at a side chain are described in, for example,JP-A-H05-32946 and JP-A-H08-27239.

The thickness of the PSA layer 3 may vary depending on the material, andis generally in the range of about 3 to 100 μm, and preferably about 10to 50 μm.

The protective sheet 11 may be formed by applying the above PSA on thesubstrate 2 in an appropriate thickness with use of a known applicatorsuch as a roll coater, a knife coater, a roll knife coater, a reversecoater or a die coater, followed by drying to produce the PSA layer 3.Alternatively, the PSA layer 3 may be formed on a release film andtransferred onto the substrate 2.

Next, the second protection structure according to the present inventionwill be explained. The second protection structure corresponds to thefirst protection structure in which the substrate 2 has pluralstructural layers. Hereinbelow, two of the structural layers of thesubstrate 2 will be referred to as the “first protective layer 1” andthe “second protective layer 2”.

The first protective layer 1 and the second protective layer 2 may becomposed of the same or different kinds of rigid films. A combination ofa rigid film and another type of film is also possible. It isparticularly preferred that the first protective layer 1 which faces thewafer side is formed of a stress relaxation film described later, andthe second protective layer 2 which is positioned at the opposite sideto the wafer is formed of a rigid film.

An example of the second protection structure is a protection structureB as shown in FIG. 2, which includes the semiconductor wafer 5 and thelaminated protective sheet 12 overlaid on the circuit surface of thesemiconductor wafer. The laminated protective sheet 12 comprises thefirst protective layer 1 having a larger diameter than the outerdiameter of the semiconductor wafer and the second protective layer 2laminated on the first protective layer 1 and having an outer diameterthat is equal to the outer diameter of the first protective layer 1. Thelaminated protective sheet is overlaid on the circuit surface via theside of the first protective layer 1.

Another example of the second protection structure is a protectionstructure C as shown in FIG. 3, which includes the semiconductor wafer 5and the laminated protective sheet 13 overlaid on the circuit surface ofthe semiconductor wafer. The laminated protective sheet 13 comprises thefirst protective layer 1 having substantially the same size as the outerdiameter of the semiconductor wafer and the second protective layer 2laminated on the first protective layer 1 and having an outer diameterthat is larger than the outer diameter of the first protective layer 1.The laminated protective sheet is overlaid on the circuit surface viathe side of the first protective layer 1.

The upper surface of the second protective layer 2 is provided with theadhesive layer 4 for lamination with the first protective layer 1. Thefirst protective layer 1 and the second protective layer 2 may be bondedfirmly to avoid separation, or may be separably laminated.

The adhesives for firmly bonding the first and the second protectivelayers 1 and 2 include rubber-based and acryl-based permanent-bondingPressure-sensitive adhesives and polyester-based and polyamide-based drylaminating adhesives. The adhesives for separably laminating the firstand the second protective layers 1 and 2 include the above-mentionedPressure-sensitive adhesives for the PSA layer 3. The thickness of theadhesive layer 4 may vary depending on the material, and is generally inthe range of about 1 to 100 μm, and preferably about 3 to 50 μm.

Preferably, the adhesive layer 4 is of the same size (flush) as thesecond protective layer 2. In the case of the protection structure C,the adhesive layer 4 may be of the same size as the first protectivelayer 1.

In the protection structure B, the first protective layer 1 and thesecond protective layer 2 are of substantially the same size. Thedifference in outer diameter between the laminated protective sheet 12and the semiconductor wafer 5 ((outer diameter of the laminatedprotective sheet 12)−(outer diameter of the semiconductor wafer 5)) ispreferably in the range of 0.1 to 10 mm, more preferably 0.1 to 5 mm,and particularly preferably 0.1 to 2 mm.

In the protection structure C, the first protective layer 1 has an areasuch that it can cover the circuit surface of the semiconductor wafer.The edge of the semiconductor wafer has been ground slantingly forpreventing breakage and the circuit surface is formed inside the trimmedcontour. Therefore, it is preferred that the outer diameter of the firstprotective layer 1 is equal to or slightly smaller than the outerdiameter of the semiconductor wafer 5. Specifically, the difference inouter diameter between the first protective layer 1 and thesemiconductor wafer 5 ((outer diameter of the first protective layer1)−(outer diameter of the semiconductor wafer 5)) is preferably in therange of −2 to 0 mm, particularly preferably −1.5 to 0 mm, and optimally−1.0 to 0 mm.

On the other hand, the outer diameter of the second protective layer 2is slightly larger than the outer diameter of the semiconductor wafer 5.Specifically, the difference in outer diameter between the secondprotective layer 2 and the semiconductor wafer 5 ((outer diameter of thesecond protective layer 2)−(outer diameter of the semiconductor wafer5)) is preferably in the range of +0.1 to +10 mm, more preferably +0.1to +5 mm, still preferably +0.1 to +2 mm, particularly preferably +0.1to +1.5 mm, and optimally +0.1 to +1 mm.

Accordingly, the difference in outer diameter between the secondprotective layer 2 and the first protective layer 1 ((outer diameter ofthe second protective layer 2)−(outer diameter of the first protectivelayer 1)) is preferably in the range of +0.1 to +12 mm, more preferably+0.1 to +6 mm, still preferably +0.1 to +4 mm, particularly preferably+0.1 to +3 mm, and optimally +0.1 to +2 mm.

It is particularly preferred that the first protective layer 1 includesa stress relaxation film described later, and the second protectivelayer 2 includes the aforementioned rigid film.

The semiconductor wafer 5 is supported on the first protective layer 1.When the first protective layer 1 has self-adhesive properties, thesemiconductor wafer 5 may be supported on the first protective layer 1without forming any PSA. It is also possible that the semiconductorwafer 5 is supported via the abovementioned PSA 3.

The first protective layer 1 preferably includes a stress relaxationfilm.

The stress relaxation film has excellent stress relaxation properties.Specifically, a tensile test of the film shows a stress relaxation rateafter 1 minute of 10% elongation of 40% or above, preferably 50% orabove, and more preferably 60% or above. The higher the stressrelaxation rate, the more preferable. The upper limit of the stressrelaxation rate is theoretically 100%, and may be 99.9%, 99% or 95%depending on conditions.

The stress relaxation film has excellent stress relaxation propertiessuch that the residual stress is attenuated immediately after the filmis applied to the wafer 5. Accordingly, even when the wafer to which thelaminated protective sheet 12 or 13 has been applied is ground to anultrathin thickness and consequently becomes brittle, the wafer can besupported without curvature because of very small residual stress in thelaminated protective sheet as a whole.

The thickness of the stress relaxation film is preferably in the rangeof 30 to 1000 μm, more preferably 50 to 800 μm, and particularlypreferably 80 to 500 μm.

The stress relaxation film is not particularly limited as long as it isa resin film satisfying the above properties. Resins capable ofsatisfying the above properties, and resins containing appropriateadditives so as to achieve the properties are employable. The stressrelaxation film may be a cured film of a hardening resin or a film of athermoplastic resin.

The hardening resins include photocurable resins and thermosettingresins. The photocurable resins are preferably employed.

As the photocurable resins, resin compositions based onphotopolymerizable urethane acrylate oligomers are preferably used. Theurethane acrylate oligomers suited for use in the present inventionpreferably range in molecular weight from 1000 to 50000, and morepreferably from 2000 to 30000. The urethane acrylate oligomers may beused singly or in combination of two or more kinds.

The use of the urethane acrylate oligomer alone often results indifficult film production. Therefore, the oligomer is generally dilutedwith a photopolymerizable monomer, and the mixture is formed into acoating film and cured to give a film. The photopolymerizable monomerhas a photopolymerizable double bond in the molecule. In the invention,acryl ester compounds having a relatively bulky group, such as isobornyl(meth)acrylate, dicyclopentenyl (meth)acrylate and phenylhydroxypropylacrylate are particularly preferred.

The photopolymerizable monomer is preferably used in an amount of 5 to900 parts by weight, more preferably 10 to 500 parts by weight, andparticularly preferably 30 to 200 parts by weight per 100 parts byweight of the urethane acrylate oligomer.

When the stress relaxation film is formed from the photocurable resin,the resin may be mixed with a photopolymerization initiator forreduction of polymerization curing time by irradiation and dose.

The amount of the photopolymerization initiator is preferably in therange of 0.05 to 15 parts by weight, more preferably 0.1 to 10 parts byweight, and particularly preferably 0.5 to 5 parts by weight per 100parts by weight of all the resins combined.

An appropriate combination may be selected from various combinations ofthe oligomers and the monomers so as to produce the hardening resinscapable of satisfying the aforesaid properties.

The resins may contain additives, including inorganic fillers such ascalcium carbonate, silica and mica, metal fillers such as iron and lead,and colorants such as pigments and dyes.

To produce the stress relaxation film, the liquid resin (uncured resin,solution of the resin, etc.) may be cast in a small thickness over acasting film and be produced into a film (by curing or drying) throughpredetermined means, followed by removal of the casting film. Thisprocess will not cause the resin to undergo high stress during filmformation and rarely results in fish eyes. Furthermore, the processpermits high uniformity of film thickness, with the thickness accuracybeing generally within 2%.

Other processes for producing the stress relaxation films includeextrusion with use of a T-die or an inflation, and calendering.

To achieve higher adhesion with the PSA layer 3, the upper surface ofthe first protective layer 1 may be corona treated or may be overlaidwith a layer such as a primer coat. The PSA layer 3 is as described withrespect to the first protection structure A.

The semiconductor wafer protection structures according to the presentinvention are suitably adopted to storage, transportation and processingof ultrathin semiconductor wafers. Particularly, the protectionstructures are useful for the protection of the circuit surface duringbackgrinding the wafer to an ultrathin thickness, and for storage andtransportation of the ultrathin wafers.

When a semiconductor wafer is subjected to a backgrinding step using theprotection structure A, the protective sheet 11 is applied to thecircuit surface of the semiconductor wafer 5 and backgrinding isperformed by a conventional method.

When a semiconductor wafer is subjected to a backgrinding step using theprotection structure B or C, the laminated protective sheet 12 or 13 isapplied to the surface of the wafer 5 via the PSA layer 3. The surfaceof the wafer 5 is provided with a circuit pattern. The application isperformed by use of a laminator specialized for wafer manufacturingwhile adding as small tension as possible. However, since application ispractically impossible without any tension at all, the tension oftenaccumulates in usual PSA sheets as residual stress. In the invention,the use of the stress relaxation film as the first protective layer 1provides stress relaxation so that the internal stress can be reduced.The rigid films are less susceptible to tension from application andsuffer little residual internal stress.

When the laminated protective sheet is employed, the first protectivelayer 1 may be applied to the circuit surface of the wafer 5 and thesecond protective layer 2 may be applied to the exposed surface of thefirst protective layer 1. It is also possible that the first protectivelayer 1 and the second protective layer 2 are previously laminated andthe resultant laminated protective sheet is overlaid on the circuitsurface of the wafer 5 via the side of the first protective layer 1.

In the latter case, the first protective layer 1 and the secondprotective layer 2 may be supplied as a laminated sheet precut intopredetermined size, or may be supplied as uncut laminated sheet and becut into predetermined size after applied to the wafer 5. In thepreferred embodiment of the protection structure C, the first protectivelayer 1 is supplied as an uncut sheet, is applied to the wafer 5, and iscut with a cutter knife along the edge of the wafer 5; subsequently, thesecond protective layer 2 is supplied as a sheet precut intopredetermined size and is laminated on the first protective layer 1 soas to align the centers of the wafer 5 and the second protective layer2. Thus, the protection structure C for semiconductor wafer according tothe present invention can be fabricated with high precision.

While the semiconductor wafer is protected with the protection structureas described above, the back surface of the wafer is ground with agrinder or the like until a predetermined thickness is reached,optionally followed by chemical polishing by etching or the like.

The wafer may be ground to a thickness of, for example, 30 to 100 μm. Asdescribed above, the usual PSA sheets suffer residual stress as a resultof accumulation of tension at the time of application, and the ultrathinwafers are often caused to warp. In the invention, the use of the stressrelaxation film provides stress relaxation so that the internal stresscan be reduced. Accordingly, the wafer will not be warped even if groundto an ultrathin thickness.

After completion of the grinding step as described above, the wafers 5are stored in a wafer cassette and transported to the next step. Sincethe maximum diameter of the protective sheet 11 or the laminatedprotective sheet 12 or 13 is slightly larger than that of the wafer 5,the semiconductor wafer protection structure stored in the wafercassette can prevent the edge of the wafers 5 from direct contact withthe sidewalls of the cassette. Accordingly, the wafer can be transportedwithout damage. Namely, the end portion of the protective sheetfunctions as cushion to protect the wafer 5.

After transportation and storage, the semiconductor wafer is subjectedto a dicing step. Prior to the dicing step, the adhesive sheet 6 isoften applied to the ground surface (back surface of the circuitsurface) of the wafer for various purposes such as formation of adie-bonding adhesive layer. After the adhesive sheet 6 is applied, theprotective sheet or the laminated protective sheet is removed totransfer the wafer to the adhesive sheet 6. The adhesive sheet usedherein may be selected without limitation from adhesive sheets havingvarious functions, including die-bonding sheets and semiconductorprocessing adhesive sheets.

When the adhesive sheet 6 has no functions as a dicing tape (nofunctions for fixing the wafer or picking up the chips), the adhesivesheet 6 having substantially the same size as the wafer is applied tothe wafer; thereafter a dicing tape is applied to the exposed surface ofthe adhesive sheet and the laminate is subjected to the dicing step. Theadhesive sheet 6 having substantially the same size as the wafer may beproduced by previously cutting the sheet into the size beforeapplication to the wafer. Most frequently, however, the adhesive sheet 6in the form of uncut tape is applied to the wafer and is cut along theouter periphery of the wafer.

When the semiconductor wafer is protected with the protection structureof the present invention, the wafer 5 is securely protected and is notdamaged even during application of the adhesive sheet 6 to the groundsurface of the semiconductor wafer 5. Furthermore, as illustrated inFIG. 4, an outer peripheral portion of the adhesive sheet 6 is cut in amanner such that a cutter is moved along the outer peripheral endsurface of the protective sheet. That is, the cutting blade 7 is notcontacted with the wafer's end surface. Accordingly, damage to the wafercan be reduced during application and cutting of the adhesive sheet.

Subsequently, the protective sheet or the laminated protective sheet isremoved, and thereby the wafer is transferred to the adhesive sheet 6.Thereafter, conventional steps such as dicing are performed to producesemiconductor devices.

When the adhesive layer 4 is composed of a removable adhesive, it ispreferable that the adhesive sheet 6 is applied to the wafer's groundsurface and the outer peripheral portion of the adhesive sheet is cutoff; thereafter, the second protective layer 2 is removed and, prior tothe dicing, the first protective layer 1 is removed from the wafersurface. Separate removing steps for the second protective layer 2 andthe first protective layer 1 enable reduction of flexure stress to thewafer as compared to collective release of the first and the secondprotective layers 1 and 2.

After the first and the second protective layers 1 and 2 are bothremoved and thereby the wafer is transferred to the dicing tape, thewafer is diced by a conventional method into semiconductor chips, whichare manufactured into semiconductor devices by a conventional process.

The laminated protective sheet for semiconductor wafer according to thepresent invention is the laminated protective sheet 13 used in theprotection structure C.

That is, the laminated protective sheet 13 for semiconductor wafer is alaminate of the first and the second protective layers 1 and 2 in whichthe second protective layer 2 is larger in outer diameter than the firstprotective layer 1.

Preferred embodiments of the laminated protective sheet forsemiconductor wafer are the same as described for the aforementionedsemiconductor wafer protection structures.

INDUSTRIAL APPLICABILITY

The semiconductor wafer protection structures and methods, and thelaminated protective sheet for use therein enable prevention of damageto a wafer during grinding and transportation when the wafer is groundto an ultrathin thickness and transported.

According to the process for processing a semiconductor wafer asdescribed above, a semiconductor wafer is not damaged when an adhesivesheet is applied thereto, and the wafer's end surface is prevented fromcontact with a cutting blade when an outer peripheral portion of theadhesive sheet is cut off. Therefore, the probability that the waferwill be damaged during application and cutting of the adhesive sheet canbe reduced.

EXAMPLES

Hereinbelow, the present invention will be described in greater detailby Examples. However, it should be construed that the invention is notlimited thereto.

The “wafer transportation ability” and “adhesive sheet applying ability”were evaluated by the methods described below.

(Wafer Transportation Ability)

In Examples and Comparative Examples, respective semiconductor waferprotection structures were produced. Then, the silicon wafers wereground to thickness of 50 μm by means of a wafer grinder (grinder DFGseries manufactured by DISCO CORPORATION). The wafer protectionstructures were then stored in a wafer cassette case with use of a wafercarrier exchanger (Adwill RAD-CXV manufactured by LINTEC CORPORATION)Subsequently, the wafer cassette case was manually transported andinstalled into a cassette house of a dicing tape mounter (AdwillRAD-2500 series manufactured by LINTEC CORPORATION).

Ten 8-inch (200 mm) wafers were processed in each Example or ComparativeExample, and evaluation was performed by counting the number of crackedwafer edges or damaged wafers.

(Adhesive Sheet Applying Ability)

In Examples and Comparative Examples, respective semiconductor waferprotection structures were produced. Then, the silicon wafers wereground to thickness of 50 μm by means of a wafer grinder (grinder DFGseries manufactured by DISCO CORPORATION). An adhesive sheet (Adwill LPseries manufactured by LINTEC CORPORATION) was laminated on the groundsurface of the wafer while protecting another surface with theprotective sheet, using laminator Adwill RAD-3500 series (manufacturedby LINTEC CORPORATION). The lamination of the adhesive sheet wasperformed under heating at about 150° C. to increase adhesion of theadhesive sheet to the wafer's ground surface. Thereafter, the adhesivesheet was cut into a predetermined size by moving a knife along thewafer configuration.

Ten 8-inch (200 mm) wafers were processed in each Example or ComparativeExample, and evaluation was performed by counting the number of waferscracked or damaged during lamination of the adhesive sheet.

Example 1

(1) Stress Relaxation Film

50 Parts by weight of an urethane acrylate oligomer having aweight-average molecular weight of 5000 (manufactured by ARAKAWACHEMICAL INDUSTRIES, LTD.), 25 parts by weight of isobornyl acrylate, 25parts by weight of phenylhydroxypropyl acrylate, 2.0 parts by weight ofa photopolymerization initiator (IRGACURE 184 manufactured by CIBASPECIALTY CHEMICALS) and 0.2 part by weight of phthalocyanine pigmentwere mixed together to give a photocurable resin composition as amaterial for forming a stress relaxation film.

The resin composition thus obtained was applied over apolyethyleneterephthalate (PET) film (product of Toray Industries, Inc.,thickness: 38 μm), in a thickness of 110 μm by the fountain die method.Thus, a resin composition layer was formed. Immediately after theapplication, the same PET film was laminated on the resin compositionlayer, and the laminate was UV irradiated at a dose of 250 mJ/cm² withuse of a high-pressure mercury lamp (160 W/cm, height: 10 cm) thereby tocrosslink and cure the resin composition layer. The PET films on theboth surfaces were removed. Thus, a stress relaxation film was obtainedwhich had a thickness of 110 μm, a stress relaxation rate of 87%, and aYoung's modulus of 1.8×10⁸ Pa.

(2) Pressure-Sensitive Adhesive for Sticking to Wafer's Circuit Surface

An energy radiation-curable copolymer having an energy radiationpolymerizable group at a side chain was compounded with 5 parts byweight of a curing agent (addition product of toluylene diisocyanate andtrimethylolpropane) and 5 parts by weight a photopolymerizationinitiator (IRGACURE 184 manufactured by CIBA SPECIALTY CHEMICALS) toprepare a PSA. The above energy radiation-curable copolymer had beenobtained by reaction of 100 parts by weight of a copolymer thatconsisted of 85 parts by weight of n-butyl acrylate and 15 parts byweight of 2-hydroxyethyl acrylate and had a weight-average molecularweight of about 650000, with 16 parts by weight of methacryloyloxyethylisocyanate. The thus-obtained PSA was applied to a PET release film(SP-PET 3801 manufactured by LINTEC CORPORATION, thickness: 38 μm) withuse of a roll knife coater so as to achieve a dry thickness of 15 μm,followed by drying. The resultant adhesive layer was transferred to thestress relaxation film prepared in (1). Thus, a first protective layer 1was prepared.

(3) Second Protective Layer

An acrylic permanent-bonding type PSA (PK manufactured by LINTECCORPORATION) was applied to a PET release film (SP-PET 3801 manufacturedby LINTEC CORPORATION, thickness: 38 μm) so as to achieve a drythickness of 20 μm, followed by drying. The resultant adhesive layer wastransferred to a rigid PET film (product of Toray Industries, Inc.,thickness: 125 μm, Young's modulus: 4.9×10⁹ Pa, value ofthickness×Young's modulus: 6.1×10⁵ N/m). Thus, a second protective layerwas prepared.

(4) Configuration of Laminated Protective Sheet

The second protective layer was precut into a circular form 201 mm indiameter. The release film on the first protective layer was peeled, andthe first protective layer was laminated to the mirror surface of asilicon wafer (200 mm in diameter, 750 μm in thickness) via the exposedPSA with use of a tape laminator (Adwill RAD 3500/m12 manufactured byLINTEC CORPORATION). The first protective layer was cut along thecontour of the silicon wafer. The cutting was performed while tilting acutter at an angle of about 15° relative to the vertical surface of thefirst protective layer. As a result, the diameter of the surface offirst protective layer became 199.9 mm.

Thereafter, the exposed surface of the first protective layer waslaminated with the second protective layer via the PSA layer with centeralignment. Thus, a semiconductor wafer protection structure wasfabricated.

Example 2

The first and the second protective layers produced in Example 1 (1) to(3) were cut into circular forms 199.5 mm and 201 mm in diameterrespectively. The release film on the second protective layer waspeeled, and the second protective layer was laminated to the stressrelaxation film of the first protective layer, via the exposed PSA withcenter alignment. Thus, a laminated protective sheet was produced.Subsequently, the laminated protective sheet was laminated to the mirrorsurface of a silicon wafer via the PSA layer of the first protectivelayer with center alignment. Thus, a semiconductor wafer protectionstructure was fabricated.

Examples 3-5

The first and the second protective layers produced in Example 1 (1) to(3) were laminated in a manner such that the release film on the secondprotective layer was peeled and the second protective layer waslaminated to the stress relaxation film of the first protective layer,via the exposed PSA. The resultant laminated protective sheet was precutinto a circular form 201 mm in diameter. Subsequently, the laminatedprotective sheet was laminated to the mirror surface of a silicon wafervia the PSA layer of the first protective layer with center alignment.Thus, a semiconductor wafer protection structure was fabricated (Example3). Semiconductor wafer protection structures 205 mm and 208 mm indiameter of the laminated protective sheet were produced in a similarmanner in Examples 4 and 5 respectively.

Examples 6-7

The first and the second protective layers produced in Example 1 (1) to(3) were laminated in a manner such that the release film on the secondprotective layer was peeled and the second protective layer waslaminated to the stress relaxation film of the first protective layer,via the exposed PSA. The resultant laminated protective sheet waslaminated to the mirror surface of a silicon wafer via the PSA layer ofthe first protective layer with center alignment. Thereafter, thelaminated protective sheet was cut such that the outer diameter acrossthe center of the wafer became 201 mm. Thus, a semiconductor waferprotection structure was fabricated (Example 6). In Example 7, asemiconductor wafer protection structure having a laminated protectivesheet diameter of 208 mm was produced in a similar manner.

Example 8

The PSA employed in Example 1(2) was applied to a PET release film(SP-PET 3801 manufactured by LINTEC CORPORATION, thickness: 38 μm) so asto achieve a dry thickness of 20 μm, followed by drying. The resultantadhesive layer was transferred to a rigid PET film (product of TorayIndustries, Inc., thickness: 125 μm, Young's modulus: 4.9×10⁹ Pa, valueof thickness×Young's modulus: 6.1×10⁵ N/m). Thus, a protective sheet wasprepared. Thereafter, the protective sheet was precut into a circularform 205 mm in diameter. Subsequently, the protective sheet waslaminated to the mirror surface of a silicon wafer with centeralignment. Thus, a semiconductor wafer protection structure wasfabricated.

Example 9

The PSA employed in Example 1(2) was applied to a PET release film(SP-PET 3801 manufactured by LINTEC CORPORATION, thickness: 38 μm) so asto achieve a dry thickness of 20 μm, followed by drying. The resultantadhesive layer was transferred to a rigid PET film (product of TorayIndustries, Inc., thickness: 125 μm, Young's modulus: 4.9×10⁹ Pa, valueof thickness×Young's modulus: 6.1×10⁵ N/m). Thus, a protective sheet wasprepared. Thereafter, the protective sheet was laminated to the mirrorsurface of a silicon wafer with center alignment. Subsequently, theprotective sheet was cut such that the outer diameter across the centerof the wafer became 205 mm. Thus, a semiconductor wafer protectionstructure was fabricated.

Comparative Example 1

The release film on the second protective layer produced in Example 1(3) was peeled, and the second protective layer was laminated to thestress relaxation film of the first protective layer produced in Example1 (1) to (2), via the exposed PSA layer. Thus, a laminated protectivesheet was prepared. Subsequently, the laminated protective sheet waslaminated to the mirror surface of a silicon wafer with use of a tapelaminator, and was cut along the contour of the silicon wafer. Thus, asemiconductor wafer protection structure was fabricated. The diameter ofthe uppermost substrate surface of the protective sheet was 199.8 mm.

Comparative Example 2

The first protective layer produced in Example 1 (1) to (2) waslaminated to the mirror surface of a silicon wafer via the PSA layerwith center alignment. Thereafter, the protective layer was cut alongthe contour of the silicon wafer. Thus, a semiconductor wafer protectionstructure was fabricated. The diameter of the uppermost substratesurface of the protective sheet was 199.8 mm.

The constitution of Examples and Comparative Examples is shown in Table1, and the evaluation results in Table 2. TABLE 1 Second protectivelayer First protective layer Thkns. X Adhesive Stress UV PSA Young'sYoung's layer^(*1)) Thkns. relaxation thickness Thkns. modulus modulusType/ Application Cutting (μm) rate (%) (μm) (μm) (Pa) N/m Thkns.method^(*2)) method^(*3)) Ex. 1 110 87 UV type PET 125 4.9 × 10⁹ 6.1 ×10⁵ PK Two-time only 2^(nd) 15 μm 20 μm lamination protective layerprecut: 201 nm Ex. 2 110 87 UV type PET 125 4.9 × 10⁹ 6.1 × 10⁵ PKOne-time 1^(st): 199.5 nm 15 μm 20 μm lamination 2^(nd): 201 nm Ex. 3110 87 UV type PET 125 4.9 × 10⁹ 6.1 × 10⁵ PK One-time Precut: 201 nm 15μm 20 μm lamination Ex. 4 110 87 UV type PET 125 4.9 × 10⁹ 6.1 × 10⁵ PKOne-time Precut: 205 nm 15 μm 20 μm lamination Ex. 5 110 87 UV type PET125 4.9 × 10⁹ 6.1 × 10⁵ PK One-time Precut: 208 nm 15 μm 20 μmlamination Ex. 6 110 87 UV type PET 125 4.9 × 10⁹ 6.1 × 10⁵ PK One-timeAfter cut: 201 15 μm 20 μm lamination nm Ex. 7 110 87 UV type PET 1254.9 × 10⁹ 6.1 × 10⁵ PK One-time After cut: 208 15 μm 20 μm lamination nmEx. 8 — — — PET 125 4.9 × 10⁹ 6.1 × 10⁵ UV type One-time Precut: 205 nm20 μm lamination Ex. 9 — — — PET 125 4.9 × 10⁹ 6.1 × 10⁵ UV typeOne-time After cut: 205 20 μm lamination nm Comp. 110 87 UV type PET 1254.9 × 10⁹ 6.1 × 10⁵ PK One-time After cut: Ex. 1 15 μm 20 μm lamination199.8 nm Comp. 160 87 UV type — — — One-time After cut: Ex. 2 20 μmlamination 199.8 nmThkns.: Thickness^(*1))PK (permanent-bonding type PSA), UV type (UV curable PSA)^(*2))Two-time lamination (The first protective layer was laminated onthe wafer, and then the second protective layer was laminated on thefirst protective layer.) One-time lamination (The second protectivelayer was laminated on the first protective layer, and then the laminatewas laminated on the wafer via the side of the first protective layer.In Examples 8 and 9 and Comparative Example 2, a single-layer film waslaminated.)^(*3))Precut (Cut into a predetermined size before lamination) After cut(cut into a predetermined size after lamination) 1^(st) = Firstprotective layer, 2^(nd) = Second protective layer

TABLE 2 Result of Wafer Adhesive grinding transportation sheet applyingto 50 μm properties properties Remarks Ex. 1 10/10 10/10 no 10/10 nosuccessful damaged wafer damaged wafer Ex. 2 10/10 10/10 no 10/10 nosuccessful damaged wafer damaged wafer Ex. 3 10/10 10/10 no 10/10 nosuccessful damaged wafer damaged wafer Ex. 4 10/10 10/10 no 10/10 nosuccessful damaged wafer damaged wafer Ex. 5 10/10 10/10 no 10/10 nosuccessful damaged wafer damaged wafer Ex. 6 10/10 10/10 no 10/10 nosuccessful damaged wafer damaged wafer Ex. 7 10/10 10/10 no 10/10 nosuccessful damaged wafer damaged wafer Ex. 8 10/10 10/10 no 10/10 nosuccessful damaged wafer damaged wafer Ex. 9 10/10 10/10 no 10/10 nosuccessful damaged wafer damaged wafer Comp. 10/10 7/10 three 5 of 10Wafer damaged Ex. 1 successful damaged wafers damaged wafers damagedduring Comp. 10/10 6/10 four 7 of 10 adhesive Ex. 2 successful damagedwafers sheet wafers damaged cutting

1. A semiconductor wafer protection structure, comprising a semiconductor wafer and a protective sheet overlaid on a circuit surface of the semiconductor wafer, wherein the protective sheet has a larger diameter than the outer diameter of the semiconductor wafer.
 2. A semiconductor wafer protection structure, comprising a semiconductor wafer and a laminated protective sheet overlaid on a circuit surface of the semiconductor wafer, wherein the laminated protective sheet comprises a first protective layer having substantially the same size as the outer diameter of the semiconductor wafer and a second protective layer laminated on the first protective layer and having an outer diameter that is equal to or larger than the outer diameter of the first protective layer, and the laminated protective sheet is overlaid on the circuit surface via the side of the first protective layer.
 3. The semiconductor wafer protection structure according to claim 1, wherein the protective sheet or the laminated protective sheet has a maximum diameter that is larger than the outer diameter of the semiconductor wafer by +0.1 to 10 mm.
 4. The semiconductor wafer protection structure according to claim 2, wherein the first protective layer has an outer diameter that is smaller than the outer diameter of the semiconductor wafer by −2.0 to 0 mm and the second protective layer has an outer diameter that is larger than the outer diameter of the semiconductor wafer by +0.1 to +2.0 mm.
 5. The semiconductor wafer protection structure according to claim 2, wherein the first protective layer includes a film having a stress relaxation rate of at least 40% after 1 minute of 10% elongation, and the second protective layer includes a film having a value of Young's modulus×thickness of at least 5.0×10⁴ N/m.
 6. A semiconductor wafer protection method, comprising overlaying a circuit surface of a semiconductor wafer with a protective sheet having a larger diameter than the outer diameter of the semiconductor wafer.
 7. A semiconductor wafer protection method, comprising overlaying a circuit surface of a semiconductor wafer with a laminated protective sheet, wherein the laminated protective sheet comprises a first protective layer having substantially the same size as the outer diameter of the semiconductor wafer and a second protective layer laminated on the first protective layer and having an outer diameter that is equal to or larger than the outer diameter of the first protective layer, and the laminated protective sheet is overlaid on the circuit surface via the side of the first protective layer.
 8. The semiconductor wafer protection method according to claim 6, wherein the protective sheet or the laminated protective sheet has a maximum diameter that is larger than the outer diameter of the semiconductor wafer by +0.1 to 10 mm.
 9. The semiconductor wafer protection method according to claim 7, wherein the first protective layer has an outer diameter that is smaller than the outer diameter of the semiconductor wafer by −2.0 to 0 mm and the second protective layer has an outer diameter that is larger than the outer diameter of the semiconductor wafer by +0.1 to +2.0 mm.
 10. The semiconductor wafer protection method according to claim 7, wherein the first protective layer includes a film having a stress relaxation rate of at least 40% after 1 minute of 10% elongation, and the second protective layer includes a film having a value of Young's modulus×thickness of at least 5.0×10⁴ N/m.
 11. A laminated protective sheet for semiconductor wafer comprising a first protective layer and a second protective layer, wherein the second protective layer has a larger outer diameter than that of the first protective layer.
 12. The laminated protective sheet for semiconductor wafer according to claim 11, wherein the second protective layer has an outer diameter that is larger than the outer diameter of the first protective layer by +0.1 to +4.0 mm.
 13. The laminated protective sheet for semiconductor wafer according to claim 12, wherein the first protective layer includes a film having a stress relaxation rate of at least 40% after 1 minute of 10% elongation, and the second protective layer includes a film having a value of Young's modulus×thickness of at least 5.0×10⁴ N/m.
 14. A process for processing a semiconductor wafer, comprising a step comprising backgrinding a semiconductor wafer and applying an adhesive sheet to the ground surface while protecting the semiconductor wafer by the semiconductor wafer protection method of claim
 6. 15. The process for processing a semiconductor wafer according to claim 14, comprising a further step comprising cutting off an outer peripheral portion of the adhesive sheet with a cutter in a manner such that the cutter is moved along an outer peripheral end surface of the protective sheet or the laminated protective sheet.
 16. The semiconductor wafer protection structure according to claim 2, wherein the protective sheet or the laminated protective sheet has a maximum diameter that is larger than the outer diameter of the semiconductor wafer by +0.1 to 10 mm.
 17. The semiconductor wafer protection structure according to claim 4, wherein the first protective layer includes a film having a stress relaxation rate of at least 40% after 1 minute of 10% elongation, and the second protective layer includes a film having a value of Young's modulus×thickness of at least 5.0×10⁴ N/m.
 18. The semiconductor wafer protection method according to claim 7, wherein the protective sheet or the laminated protective sheet has a maximum diameter that is larger than the outer diameter of the semiconductor wafer by +0.1 to 10 mm.
 19. The semiconductor wafer protection method according to claim 9, wherein the first protective layer includes a film having a stress relaxation rate of at least 40% after 1 minute of 10% elongation, and the second protective layer includes a film having a value of Young's modulus×thickness of at least 5.0×10⁴ N/m.
 20. The laminated protective sheet for semiconductor wafer according to claim 12, wherein the first protective layer includes a film having a stress relaxation rate of at least 40% after 1 minute of 10% elongation, and the second protective layer includes a film having a value of Young's modulus×thickness of at least 5.0×10⁴ N/m. 